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ltc2498 1 2498fg for more information www.linear.com/ltc2498 features applications description 24-bit 8-/16-channel s adc with easy drive input current cancellation the lt c ? 2498 is a 16- channel (8- differential ) 24- bit no latency s ? adc with easy drive technology. the pat- ented sampling scheme eliminates dynamic input current errors and the shortcomings of on-chip buffering through automatic cancellation of differential input current. this allows large external source impedances, and rail-to-rail input signals to be directly digitized while maintaining exceptional dc accuracy.the ltc2498 includes a high accuracy temperature sensor and an integrated oscillator. this device can be configured to measure an external signal ( from combinations of 16 analog input channels operating in single ended or dif - ferential modes) or its internal temperature sensor. the integrated temperature sensor offers 1/30 th c resolution and 2c absolute accuracy. the ltc2498 allows a wide common mode input range (0v to v cc ), independent of the reference voltage. any combination of single-ended or differential inputs can be selected and the first conversion after a new channel is selected is valid. access to the multiplexer output enables optional external amplifiers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift. data acquisition system with temperature compensation n up to 8 differential or 16 single-ended inputs n easy drive? technology enables rail-to-rail inputs with zero differential input current n directly digitizes high impedance sensors with full accuracy n 600nv rms noise n integrated high accuracy temperature sensor n gnd to v cc input/reference common mode range n programmable 50hz, 60hz or simultaneous 50hz/60hz rejection mode n 2 ppm inl, no missing codes n 1 ppm offset and 15ppm full-scale error n 2 x speed mode (15hz using internal oscillator) n no latency: digital filter settles in a single cycle, even after a new channel is selected n single supply 2.7v to 5.5v operation (0.8mw) n internal oscillator n tiny qfn 5mm 7mm package n direct sensor digitizer n direct temperature measurement n instrumentation n industrial process control internal sensor absolute temperature error f o ref + v cc muxout/adcin muxout/adcin 2.7v to 5.5v 10f com ref ? 24-bit ? adc with easy drive 16-channel mux temperature sensor in + in ? 2498 ta01a ch0ch1 ?? ? ?? ? ch7ch8 ch15 0.1f osc sdi sck sdo cs 4-wire spi interface temperature (c) ?55 ?30 ?5 absolute error (c) 5 43 2 1 ?4 ?3 ?2 ?1 0 120 95 70 45 20 2498 ta01b ?5 typical application l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. downloaded from: http:///
ltc2498 2 2498fg for more information www.linear.com/ltc2498 absolute maximum ratings supply voltage (v cc ) ................................... ?0.3 v to 6v analog input voltage ( ch 0 to ch 15, com ) ................. ?0.3 v to (v cc + 0.3 v) reference input voltage adcinn , adcinp , m uxoutp , muxoutn ................................ ?0.3 v to (v cc + 0.3 v) digital input voltage ...................... ?0.3 v to (v cc + 0.3 v) digital output voltage ................... ?0.3 v to (v cc + 0.3 v) operating temperature range ltc 24 98 c ................................................ 0 c to 70 c ltc 2498 i ............................................. ?40 c to 85 c ltc 2498 h .......................................... ?40 c to 125 c storage temperature range .................. ?65 c to 150 c (notes 1, 2) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , ?fs v in +fs (note 5) 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) h grade 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l l 2 1 10 12 ppm of v ref ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in ? v cc (note 14) l 0.5 2.5 v offset error drift 2.5v v ref v cc , gnd in + = in ? v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref l 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref l 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref 0.1 ppm of v ref /c pin configuration 13 14 15 16 top view 39 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd nc gndgnd gnd gnd com ch0ch1 ch2 ch3 ch4 gndref ? ref + v cc muxoutnadcinn adcinp muxoutp ch15 ch14 ch13 ch12 scksdo cs f o sdignd gnd ch5ch6 ch7 ch8 ch9 ch10ch11 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2498cuhf#pbf ltc2498cuhf#trpbf 2498 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc2498iuhf#pbf ltc2498iuhf#trpbf 2498 38-lead (5mm 7mm) plastic qfn ?40c to 85c ltc2498huhf#pbf ltc2498huhf#trpbf 2498 38-lead (5mm 7mm) plastic qfn ?40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics ( normal speed ) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) downloaded from: http:///
ltc2498 3 2498fg for more information www.linear.com/ltc2498 electrical characteristics ( normal speed ) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) electrical characteristics (2 x speed ) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , ?fs v in +fs (note 5) 24 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.2v (note 6) l 2 1 10 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in ? v cc (note 14) l 0.5 2 mv offset error drift 2.5v v ref v cc , gnd in + = in ? v cc 100 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref l 25 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref l 25 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in ? = 0.75v ref 0.1 ppm of v ref /c output noise 5v v cc 2.5v, v ref = 5v, gnd in + = in ? v cc 0.85 v rms converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in + = in ? v cc (note 5) l 140 db input common mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in ? v cc (note 5) l 140 db input common mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in ? v cc (note 5) l 140 db input normal mode rejection 50hz 2% 2.5v v ref v cc , gnd in + = in ? v cc (notes 5, 7) l 110 120 db input normal mode rejection 60hz 2% 2.5v v ref v cc , gnd in + = in ? v cc (notes 5, 8) l 110 120 db input normal mode rejection 50hz/60hz 2% 2.5v v ref v cc , gnd in + = in ? v cc (notes 5, 9) l 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in + = in ? v cc (note 5) l 120 140 db power supply rejection dc v ref = 2.5v, in + = in ? = gnd 120 db power supply rejection, 50hz 2% v ref = 2.5v, in + = in ? = gnd (notes 7, 9) 120 db power supply rejection, 60hz 2% v ref = 2.5v, in + = in ? = gnd (notes 8, 9) 120 db parameter conditions min typ max units total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 15 15 ppm of v ref ppm of v ref ppm of v ref output noise 5.5v < v cc < 2.7v, 2.5v v ref v cc , gnd in + = in ? v cc (note 13) 0.6 v rms internal ptat signal t a = 27c (note 5) 27.8 28.0 28.2 mv internal ptat temperature coefficient 93.5 v/c analog input and reference the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage ( in + corresponds to the selected positive input channel ) gnd ? 0.3v v cc + 0.3v v in ? absolute/common mode in ? voltage ( in ? corresponds to the selected negative input channel or com ) gnd ? 0.3v v cc + 0.3v v downloaded from: http:///
ltc2498 4 2498fg for more information www.linear.com/ltc2498 digital inputs and digital outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) analog input and reference the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage ( cs , f o , sdi) 2.7v v cc 5.5v (note 18) l v cc ? 0.5 v v il low level input voltage ( cs , f o , sdi) 2.7v v cc 5.5v l 0.5 v v ih high level input voltage (sck) 2.7v v cc 5.5v (notes 10, 15) l v cc ? 0.5 v v il low level input voltage (sck) 2.7v v cc 5.5v (notes 10, 15) l 0.5 v i in digital input current ( cs , f o , sdi) 0v v in v cc l ?10 10 a i in digital input current (sck) 0v v in v cc (notes 10, 15) l ?10 10 a c in digital input capacitance ( cs , f o , sdi) 10 pf c in digital input capacitance (sck) (notes 10, 17) 10 pf v oh high level output voltage (sdo) i o = ?800a (notes 10, 17) l v cc ? 0.5 v v ol low level output voltage (sdo) i o = 1.6ma (notes 10, 17) l 0.4 v v oh high level output voltage (sck) i o = ?800a l v cc ? 0.5 v v ol low level output voltage (sck) i o = 1.6ma l 0.4 v i oz hi-z output leakage (sdo) l ?10 10 a power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion current (note 12) temperature measurement (note 12) sleep mode (note 12) h-grade l l l l 160 200 1 275 300 2 2.5 a a a a symbol parameter conditions min typ max units v in input voltage range (in + ? in ? ) differential/single-ended l ?fs +fs v fs full scale of the input (in + ? in ? ) differential/single-ended l 0.5v ref v lsb least significant bit of the output code l fs/2 24 ref + absolute/common mode ref + voltage l 0.1 v cc v ref ? absolute/common mode ref ? voltage l gnd ref + ? 0.1v v v ref reference voltage range (ref + ? ref ? ) l 0.1 v cc v cs(in + ) in + sampling capacitance 11 pf cs(in ? ) in ? sampling capacitance 11 pf cs(v ref ) v ref sampling capacitance 11 pf i dc_leak(in + ) in + dc leakage current sleep mode, in + = gnd l ?10 1 10 na i dc_leak(in ? ) in ? dc leakage current sleep mode, in ? = gnd l ?10 1 10 na i dc_leak(ref + ) ref + dc leakage current sleep mode, ref + = v cc l ?100 1 100 na i dc_leak(ref ? ) ref ? dc leakage current sleep mode, ref ? = gnd l ?100 1 100 na t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db downloaded from: http:///
ltc2498 5 2498fg for more information www.linear.com/ltc2498 symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 16) l 10 1000 khz t heo external oscillator high period l 0.125 50 s t leo external oscillator low period l 0.125 50 s t conv_1 conversion time for 1x speed mode 50hz mode 60hz mode simultaneous 50/60hz mode external oscillator l l l 157.2 131 144.1 160.3 133.6 146.9 41036/f eosc (in khz) 163.5 136.3 149.9 ms ms ms ms t conv_2 conversion time for 2x speed mode 50hz mode 60hz mode simultaneous 50/60hz mode external oscillator l l l 78.7 65.6 72.2 80.3 66.9 73.6 20556/f eosc (in khz) 81.9 68.2 75.1 ms ms ms ms f isck internal sck frequency internal oscillator (note 10) external oscillator (notes 10, 11) 38.4 f eosc /8 khz khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 10) l 4000 khz t lesck external sck low period (note 10) l 125 ns t hesck external sck high period (note 10) l 125 ns t dout_isck internal sck 32-bit data output time internal oscillator external oscillator l 0.81 0.83 256/f eosc (in khz) 0.85 ms ms t dout_esck external sck 32-bit data output time (note 10) 32/f esck (in khz) ms t 1 cs to sdo low l 0 200 ns t 2 cs to sdo hi-z l 0 200 ns t 3 cs to sck internal sck mode l 0 200 ns t 4 cs to sck external sck mode l 50 ns t kqmax sck to sdo valid l 200 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns t 7 sdi setup before sck (note 5) l 100 ns t 8 sdi hold after sck (note 5) l 100 ns digital inputs and digital outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime . note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise specified. v refcm = v ref /2, f s = 0.5v ref v in = in + ? in ? , v in(cm) = (in + ? in ? )/2, where in + and in ? are the selected input channels. note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless other wise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band.note 7: 50hz mode ( internal oscillator ) or f eosc = 256 khz 2% ( external oscillator). note 8: 60hz mode (internal oscillator) or f eosc = 307.2khz 2% (external oscillator).note 9: simultaneous 50hz/60hz mode (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the sck can be configured in external sck mode or internal sck mode. in external sck mode, the sck pin is used as a digital input and the driving clock is f esck . in the internal sck mode, the sck pin is used as a digital output and the output clock signal during the data output is f isck . note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses its internal oscillator. note 13: the output noise includes the contribution of the internal calibration operations.note 14: guaranteed by design and test correlation. note 15: the converter is in external sck mode of operation such that the sck pin is used as a digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in hz. note 16: refer to applications information section for performance vs data rate graphs.note 17: the converter is in internal sck mode of operation such that the sck pin is used as a digital output.note 18: for v cc < 3v, v ih is 2.5v for pin f o . downloaded from: http:///
ltc2498 6 2498fg for more information www.linear.com/ltc2498 typical performance characteristics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) noise histogram (6.8sps) noise histogram (7.5sps) long-term adc readings input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?1.5 ?0.5 0.5 1.5 2498 g01 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c ?45c 25c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2498 g02 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?45c, 25c, 90c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?45c, 25c, 90c 2498 g03 input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?1.5 ?0.5 0.5 1.5 2498 g04 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c 25c ?45c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12?8 0 8 ?0.75 ?0.25 0.25 0.75 2498 g05 1.25 ?1.25 v cc = 5v v ref = 5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c input voltage (v) ?12 tue (ppm of v ref ) ?4 4 12 ?8 0 8 ?0.75 ?0.25 0.25 0.75 2498 g06 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c ?45c output reading (v) ?3 number of readings (%) 8 10 12 0.6 2498 g07 64 ?1.8 ?0.6 ?2.4 1.2 ?1.2 0 1.8 2 0 14 10,000 consecutivereadings v cc = 5v v ref = 5v v in = 0v t a = 25c rms = 0.60v average = ?0.69v output reading (v) ?3 number of readings (%) 8 10 12 0.6 2498 g08 64 ?1.8 ?0.6 ?2.4 1.2 ?1.2 0 1.8 2 0 14 10,000 consecutivereadings v cc = 2.7v v ref = 2.5v v in = 0v t a = 25c rms = 0.59v average = ?0.19v time (hours) 0 ?5 adc reading (v) ?3 ?1 1 10 20 30 40 2498 g09 50 3 5 ?4 ?2 0 2 4 60 v cc = 5v, v ref = 5v, v in = 0v, v in(cm) = 2.5v t a = 25c, rms noise = 0.60v downloaded from: http:///
ltc2498 7 2498fg for more information www.linear.com/ltc2498 typical performance characteristics rms noise vs input differential voltage rms noise vs v in(cm) rms noise vs temperature (t a ) rms noise vs v cc rms noise vs v ref offset error vs v in(cm) offset error vs temperature offset error vs v cc offset error vs v ref input differential voltage (v) 0.4 rms noise (ppm of v ref ) 0.6 0.8 1.00.5 0.7 0.9 ?1.5 ?0.5 0.5 1.5 2498 g10 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(cm) (v) ?1 rms noise (v) 0.8 0.9 1.0 2 4 2498 g11 0.7 0.6 0 1 3 5 6 0.5 0.4 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd t a = 25c temperature (c) ?45 0.4 rms noise (v) 0.5 0.6 0.7 0.8 1.0 ?30 ?15 15 0 30 45 60 2498 g12 75 90 0.9 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd v cc (v) 2.7 rms noise (v) 0.8 0.9 1.0 3.9 4.7 2498 g13 0.7 0.6 3.1 3.5 4.3 5.1 5.5 0.5 0.4 v ref = 2.5v v in = 0v v in(cm) = gnd t a = 25c v ref (v) 0 0.4 rms noise (v) 0.5 0.6 0.7 0.8 0.9 1.0 1 2 3 4 2498 g14 5 v cc = 5v v in = 0v v in(cm) = gnd t a = 25c v in(cm) (v) ?1 offset error (ppm of v ref ) 0.1 0.2 0.3 2 4 2498 g15 0 ?0.1 0 1 3 5 6 ?0.2 ?0.3 v cc = 5v v ref = 5v v in = 0v t a = 25c temperature (c) ?45 ?0.3 offset error (ppm of v ref ) ?0.2 0 0.1 0.2 ?15 15 30 90 2498 g16 ?0.1 ?30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2498 g17 0 ?0.1 3.1 3.5 4.3 5.1 5.5 ?0.2 ?0.3 ref + = 2.5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c v ref (v) 0 ?0.3 offset error (ppm of v ref ) ?0.2 ?0.1 0 0.1 0.2 0.3 1 2 3 4 2498 g18 5 v cc = 5v ref ? = gnd v in = 0v v in(cm) = gnd t a = 25c downloaded from: http:///
ltc2498 8 2498fg for more information www.linear.com/ltc2498 typical performance characteristics on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature conversion current vs output data rate integral nonlinearity (2x speed mode; v cc = 5v, v ref = 5v) temperature (c) ?45 ?30 300 frequency (khz) 304 310 ?15 30 45 2498 g19 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.5 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2498 g20 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c frequency at v cc (hz) 1 0 ?20?40 ?60 ?80 ?100?120 ?140 1k 100k 2498 g21 10 100 10k 1m rejection (db) v cc = 4.1v dc v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 ?140 rejection (db) ?120 ?80 ?60 ?40 0 20 100 140 2498 g22 ?100 ?20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 ?60 ?40 0 30750 2498 g23 ?80 ?100 30650 30700 30800 ?120?140 ?20 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in ? = gnd f o = gnd t a = 25c temperature (c) ?45 100 conversion current (a) 120 160 180 200 ?15 15 30 90 2498 g24 140 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = gnd sck = ncsdo = nc sdi = gnd temperature (c) ?45 0 sleep mode current (a) 0.2 0.6 0.8 1.0 2.01.4 ?15 15 30 90 2498 g25 0.4 1.6 1.81.2 ?30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = v cc sck = ncsdo = nc sdi = gnd input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?1.5 ?0.5 0.5 1.5 2498 g27 2.5 ?2 ?2.5 ?1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 25c, 90c ?45c output data rate (readings/sec) 0 supply current (a) 500450 400 350 300 250 200 150 100 2498 g26 20 10 30 v cc = 5v v cc = 3v v ref = v cc in + = gnd in ? = gnd sck = ncsdo = nc sdi = gnd cs gnd f o = ext osc t a = 25c downloaded from: http:///
ltc2498 9 2498fg for more information www.linear.com/ltc2498 offset error vs v cc (2x speed mode) offset error vs v ref (2x speed mode) psrr vs frequency at v cc (2x speed mode) typical performance characteristics integral nonlinearity (2x speed mode; v cc = 5v, v ref = 2.5v) integral nonlinearity (2x speed mode; v cc = 2.7v, v ref = 2.5v) noise histogram (2x speed mode) rms noise vs v ref (2x speed mode) offset error vs v in(cm) (2x speed mode) offset error vs temperature (2x speed mode) input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2498 g29 1.25 ?1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 90c ?45c, 25c input voltage (v) ?3 inl (ppm of v ref ) ?1 1 3 ?2 0 2 ?0.75 ?0.25 0.25 0.75 2498 g28 1.25 ?1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 90c ?45c, 25c output reading (v) 179 number of readings (%) 8 10 12 186.2 2498 g30 64 181.4 183.8 188.6 2 0 16 14 10,000 consecutivereadings v cc = 5v v ref = 5v v in = 0v gain = 256t a = 25c rms = 0.85v average = 0.184mv v ref (v) 0 rms noise (v) 0.6 0.8 1.0 4 2498 g31 0.4 0.2 0 1 2 3 5 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v in(cm) (v) ?1 180 offset error (v) 182 186 188 190 200194 1 3 4 2498 g32 184 196 198192 0 2 5 6 v cc = 5v v ref = 5v v in = 0v f o = gnd t a = 25c temperature (c) ?45 offset error (v) 200 210 220 75 2498 g33 190 180 160 ?15 15 45 ?30 90 0 30 60 170 240 230 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2 2.5 0 offset error (v) 100 250 3 4 4.5 2498 g34 50 200 150 3.5 5 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c v ref (v) 0 offset error (v) 190 200 210 3 5 2498 g35 180 170 160 1 2 4 220 230 240 v cc = 5v v in = 0v v in(cm) = gnd f o = gnd t a = 25c frequency at v cc (hz) 1 0 ?20?40 ?60 ?80 ?100?120 ?140 1k 100k 2498 g36 10 100 10k 1m rejection (db) v cc = 4.1v dc ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c downloaded from: http:///
ltc2498 10 2498fg for more information www.linear.com/ltc2498 gnd ( pins 1, 3, 4, 5, 6, 31, 32, 33): ground. multiple ground pins internally connected for optimum ground cur- rent flow and v cc decoupling. connect each one of these pins to a common ground plane through a low impedance connection. all eight pins must be connected to ground for proper operation. nc ( pin 2): no connection. this pin can be left floating or tied to gnd.com ( pin 7): the common negative input ( in ? ) for all single-ended multiplexer configurations. the voltage on ch0 to ch15 and com pins can have any value between gnd ? 0.3 v to v cc + 0.3 v. within these limits, the two selected inputs ( in + and in ? ) provide a bipolar input range (v in = in + ? in ? ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over - range and under-range output codes. ch0 to ch15 (pins 8 to 23): analog inputs. may be pro - grammed for single-ended or differential mode.muxoutp ( pin 24): positive multiplexer output. used to drive an external buffer/amplifier or can be shorted directly to adcinp. adcinp ( pin 25): positive adc input. tie to the output of a buffer/amplifier driven by muxoutp or tie directly to muxoutp.adcinn ( pin 26): negative adc input. tie to the output of a buffer/amplifier driven by muxoutn or tie directly to muxoutn.muxoutn ( pin 27): negative multiplexer output. used to drive an external buffer/amplifier or can be shorted directly to adcinn.v cc ( pin 28): positive supply voltage. bypass to gnd with a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor as close to the part as possible.ref + ( pin 29), ref ? ( pin 30): differential reference input . the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref ? , by at least 0.1 v. the differential voltage ( ref = ref + ? ref ? ) sets the full-scale range for all input channels. when performing an on-chip temperature measurement, the minimum value of ref = 2v. typical performance characteristics psrr vs frequency at v cc (2x speed mode) psrr vs frequency at v cc (2x speed mode) frequency at v cc (hz) 0 ?140 rrejection (db) ?120 ?80 ?60 ?40 0 20 100 140 2498 g37 ?100 ?20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c frequency at v cc (hz) 30600 ?60 ?40 0 30750 2498 g38 ?80 ?100 30650 30700 30800 ?120?140 ?20 rejection (db) v cc = 4.1v dc 0.7v ref + = 2.5v ref ? = gnd in + = gnd in ? = gnd f o = gnd t a = 25c pin functions downloaded from: http:///
ltc2498 11 2498fg for more information www.linear.com/ltc2498 pin functions sdi ( pin 34): serial data input. this pin is used to select the line frequency rejection mode , 1 x or 2 x mode, temperature sensor, as well as the input channel. the serial data input is applied under control of the serial clock ( sck) during the data output/input operation. the first conversion fol - lowing a new input or mode change is valid.f o ( pin 35): frequency control pin. digital input that controls the internal conversion clock rate. when f o is connected to v cc or gnd, the converter uses its internal oscillator running at 307.2 khz. the conversion clock may also be overridden by driving the f o pin with an external clock in order to change the output rate and the digital filter rejection null.cs ( pin 36): active low chip select. a low on this pin enables the digital input/output and wakes up the adc. following each conversion, the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output aborts the data transfer and starts a new conversion. sdo ( pin 37): three-state digital output. during the data output period, this pin is used as the serial data output. when the chip select pin is high, the sdo pin is in a high impedance state. during the conversion and sleep periods , this pin is used as the conversion status output. when the conversion is in progress this pin is high; once the conversion is complete sdo goes low. the conversion status is monitored by pulling cs low. sck ( pin 38): bidirectional, digital i/o , clock pin. in internal serial clock operation mode, sck is generated internally and is seen as an output on the sck pin . in external serial clock operation mode, the digital i/o clock is externally applied to the sck pin. the serial clock operation mode is determined by the logic level applied to the sck pin at power-up and during the most recent falling edge of cs . exposed pad ( pin 39): ground. this pin is ground and must be soldered to the pcb ground plane. for prototyping purposes, this pin may remain floating. downloaded from: http:///
ltc2498 12 2498fg for more information www.linear.com/ltc2498 test circuits 1.69k sdo 2498 tc01 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2498 tc02 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc figure 1. functional block diagram autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator serial interface gnd v cc ch0ch1 ?? ? ch15 com mux muxoutp muxoutn adcinpadcinn sdo sck ref + ref ? cs sdi f o (int/ext) 2498 bd + ? temp sensor functional block diagram downloaded from: http:///
ltc2498 13 2498fg for more information www.linear.com/ltc2498 timing diagram using internal sck (sck high with cs ) timing diagram using external sck (sck low with cs ) timing diagrams cs sdo sck sdi t 1 t 3 t 7 t 8 sleep t kqmax conversion data in/out t kqmin t 2 2498 td01 cs sdo sck sdi t 1 t 5 t 6 t 4 t 7 t 8 sleep t kqmax conversion data in/out t kqmin t 2 2498 td02 downloaded from: http:///
ltc2498 14 2498fg for more information www.linear.com/ltc2498 applications information converter operation converter operation cycle the ltc2498 is a multi-channel, low power, delta-sigma analog - to - digital converter with an easy to use 4- wire inter - face and automatic differential input current cancellation. its operation is made up of three states ( see figure 2). the converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/ output cycle. the 4- wire interface consists of serial data output ( sdo), serial clock ( sck), chip select ( cs ) and serial data input ( sdi).the interface, timing, operation cycle, and data output format is compatible with linear?s entire family of s converters. initially, at power - up, the ltc2498 performs a conversion . once the conversion is complete, the device enters the sleep state. while in this sleep state, if cs in high, power consumption is reduced by two orders of magnitude. the part remains in the sleep state as long as cs is high. the conversion result is held indefinitely in a static shift register while the part is in the sleep state.once cs is pulled low, the device powers up, exits the sleep mode, and enters the data input/output state. if cs is brought high before the first rising edge of sck, the device returns to the sleep state and the power is reduced. if cs is brought high after the first rising edge of sck, the data output cycle is aborted and a new conversion cycle begins. the data output corresponds to the conversion just completed. this result is shifted out on the serial data output pin ( sdo) under the control of the serial clock pin (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck ( see figure 3). the configuration data for the next conversion is also loaded into the device at this time. data is loaded from the serial data input pin ( sdi) on each rising edge of sck. the data input/output cycle is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats.through timing control of the cs and sck pins, the ltc2498 offers several flexible modes of operation ( internal or external sck and free-running conversion modes). these various modes do not require programming and do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. ease of use the ltc2498 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog inputs is straightforward. each conversion , immediately following a newly selected input or mode, is valid and accurate to the full specifications of the device. the ltc2498 automatically performs offset and full scale calibration every conversion cycle independent of the input channel selected. this calibration is transparent to the user and has no effect with the operation cycle de - scribed above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift.easy drive input current cancellation the ltc2498 combines a high precision delta-sigma adc with an automatic, differential, input current cancellation front end. a proprietary front end passive sampling network transparently removes the differential input current. this figure 2. ltc2498 state transition diagram convert sleep channel select configuration select data output power up in + = ch0, in ? = ch1 50/60hz,1x 2498 f02 cs = low and sck downloaded from: http:///
ltc2498 15 2498fg for more information www.linear.com/ltc2498 applications information enables external rc networks and high impedance sen- sors to directly interface to the ltc2498 without external amplifiers. the remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference ( see the automatic dif - ferential input current cancellation section). this unique architecture does not require on-chip buffers thereby enabling signals to swing beyond ground or up to v cc . moreover, the cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy ( full-scale + offset + linearity + drift) is maintained even with external rc networks.power-up sequence the ltc2498 automatically enters an internal reset state when the power supply voltage v cc drops below ap- proximately 2 v. this feature guarantees the integrity of the conversion result, input channel selection, and serial clock mode. when v cc rises above this threshold, the converter creates an internal power-on reset ( por) signal with a duration of approximately 4 ms. the por signal clears all internal registers. the conversion immediately following a por cycle is performed on the input channel in + = ch0, in ? = ch1, simultaneous 50 hz/60hz rejection and 1 x output rate. the first conversion following a por cycle is accurate within the specification of the device if the power supply voltage is restored to (2.7 v to 5.5 v) before the end of the por interval. a new input channel, rejection mode, speed mode, or temperature selection can be programmed into the device during this first data input/output cycle. reference voltage range this converter accepts a truly differential external reference voltage. the absolute/common mode voltage range for ref + and ref ? pins covers the entire operating range of the device ( gnd to v cc ). for correct converter operation, v ref must be positive (ref + > ref ? ) the ltc2498 differential reference input range is 0.1 v to v cc . for the simplest operation, ref + can be shorted to v cc and ref ? can be shorted to gnd. the converter out- put noise is determined by the thermal noise of the front end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converter?s effec- tive resolution . on the other hand, a decreased reference will improve the converter?s overall inl performance. input voltage range the ltc2498 input measurement range is C0.5 ? v ref to +0.5 ? v ref in both differential and single - ended configurations as shown in figure 39. highest linearity is achieved with fully differential drive and a constant common-mode voltage ( figure 39 b). other drive schemes may incur an inl error of approximately 50 ppm. this error can be calibrated out using a three point calibration and a second-order curve fit. the analog input is truly differential with an absolute, com - mon mode range for ch0 to ch15 and com input pins extending from gnd ? 0.3 v to v cc + 0.3 v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2498 converts the bipolar differential input signal v in = in + ? in ? ( where in + and in ? are the selected input channels), from ? fs = C0.5 ? v ref to + fs = 0.5 ? v ref where v ref = ref + ? ref ? . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. signals applied to the input ( ch0 to ch15, com) may extend 300 mv below ground and above v cc . in order to limit any fault current, resistors of up to 5 k may be added in series with the input. the effect of series resistance on the converter accuracy can be evaluated from the curves presented in the input current / reference current sections . in addition, series resistors will introduce a temperature dependent error due to input leakage current. a 1 na input leakage current will develop a 1 ppm offset error on a 5 k resistor if v ref = 5 v. this error has a very strong tem- perature dependency.muxout/adcin the output of the multiplexer ( muxout) and the input to the adc ( adcin) can be used to perform input signal conditioning on any of the selected input channels or simply shorted together for direct digitization. if an external ampli - downloaded from: http:///
ltc2498 16 2498fg for more information www.linear.com/ltc2498 applications information fier is used, the ltc2498 automatically calibrates both the offset and drift of this circuit and the easy drive sampling scheme enables a wide variety of amplifiers to be used. in order to achieve optimum performance, if an external amplifier is not used, short these pins directly together (adcinp to muxoutp and adcinn to muxoutn) and minimize their capacitance to ground. serial interface pins the ltc2498 transmits the conversion result, reads the input configuration, and receives a start of conversion command through a synchronous 3- or 4- wire interface. during the conversion and sleep states, this interface can be used to access the converter status. during the data output state, it is used to read the conversion result, program the input channel, rejection frequency, speed multiplier, and select the temperature sensor.serial clock input/output (sck) the serial clock pin ( sck) is used to synchronize the data input/output transfer. each bit is shifted out of the sdo pin on the falling edge of sck and data is shifted into the sdi pin on the rising edge of sck. the serial clock pin ( sck) can be configured as either a master ( sck is an output generated internally) or a slave (sck is an input and applied externally). master mode (internal sck) is selected by simply floating the sck pin. slave mode ( external sck) is selected by driving sck low during power-up and each falling edge of cs . specific details of these sck modes are described in the serial interface timing modes section. serial data output (sdo) the serial data output pin ( sdo) provides the result of the last conversion as a serial bit stream ( msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states.when cs is high, the sdo driver is switched to a high impedance state in order to share the data output line with other devices. if cs is brought low during the conversion phase, the eoc bit ( sdo pin) will be driven high. once the conversion is complete, if cs is brought low, eoc will be driven low indicating the conversion is complete and the result is ready to be shifted out of the device.chip select ( cs ) the active low cs pin is used to test the conversion status, enable i/o data transfer, initiate a new conversion, control the duration of the sleep state, and set the sck mode. at the conclusion of a conversion cycle, while cs is high, the device remains in a low power sleep state where the supply current is reduced several orders of magnitude. in order to exit the sleep state and enter the data output state, cs must be pulled low. data is now shifted out the sdo pin under control of the sck pin as described previously. a new conversion cycle is initiated either at the conclusion of the data output cycle ( all 32 data bits read) or by pulling cs high any time between the first and 32 nd rising edges of the serial clock ( sck). in this case, the data output is aborted and a new conversion begins.serial data input (sdi) the serial data input ( sdi) is used to select the input channel, rejection frequency, speed multiplier and to ac - cess the integrated temperature sensor. data is shifted into the device during the data output/input state on the rising edge of sck while cs is low. output d ata format the ltc2498 serial output stream is 32 bits long. the first bit indicates the conversion status, the second bit is always zero, and the third bit conveys sign information. the next 24 bits are the conversion result, msb first. the remaining 5 bits are sub lsbs beyond the 24- bit level that may be included in averaging or discarded without loss of resolution.bit 31 ( first output bit) is the end of conversion ( eoc ) indicator. this bit is available on the sdo pin during the conversion and sleep states whenever cs is low. this bit is high during the conversion cycle, goes low once the conversion is complete, and is hi-z when cs is high. bit 30 ( second output bit) is a dummy bit ( dmy) and is always low. downloaded from: http:///
ltc2498 17 2498fg for more information www.linear.com/ltc2498 applications information bit 29 ( third output bit) is the conversion result sign indicator ( sig). if the selected input ( v in = in + ? in ? ) is greater than 0 v, this bit is high. if v in < 0, this bit is low. bit 28 ( fourth output bit) is the most significant bit ( msb) of the result. this bit in conjunction with bit 29 also pro - vides underrange and overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below ? fs. the function of these bits is summarized in table 1. table 1. ltc2498 status bits input range bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb v in 0.5 ? v ref 0 0 1 1 0v v in < 0.5 ? v ref 0 0 1/0 0 C0.5 ? v ref v in < 0v 0 0 0 1 v in < C0.5 ? v ref 0 0 0 0 bits 28 to 5 are the 24-bit conversion result msb first.bit 5 is the least significant bit (lsb 24 ). bits 4 to 0 are sub lsbs below the 24- bit level. bits 4 to 0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock ( sck), see figure 3. whenever cs is high, sdo remains high impedance and sck is ignored. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes in real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 ( eoc ) can be captured on the first rising edge of sck. bit 30 is shifted out of the device on the first falling edge of sck. the final data bit ( bit 0) is shifted out on the on the falling edge of the 31 st sck and may be latched on the rising edge of the 32 nd sck pulse. on the falling edge of the 32 nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc ( bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in ? pins remains be- tween ?0.3 v and v cc + 0.3 v ( absolute maximum operating range) a conversion result is generated for any differential input voltage v in from ? fs = C0.5 ? v ref to + fs = 0.5 ? v ref . for differential input voltages greater than + fs, the conversion result is clamped to the value corresponding to + fs + 1 lsb. for differential input voltages below ? fs, the conversion result is clamped to the value ? fs ? 1 lsb. figure 3. channel selection, configuration selection and data output timing eoc cs sck (external) sdi sdo 2498 f03 conversion sleep data input/output conversion msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 sig bit 29 ?0? bit 30 bit 31 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd bit 18 bit 17 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 don't care don't care hi-z hi-z downloaded from: http:///
ltc2498 18 2498fg for more information www.linear.com/ltc2498 applications information input d ata format the ltc2498 serial input word is 13 bits long and contains two distinct sets of data. the first set ( sgl, odd, a2, a1, a0) is used to select the input channel. the second set of data ( im, fa , fb, spd) is used to select the frequency rejec - tion, speed mode (1 x , 2 x), and temperature measurement. after power-up, the device initiates an internal reset cycle which sets the input channel to ch 0 ? ch 1 ( in + = ch0, in ? = ch1), the frequency rejection to simultaneous 50 hz/60hz, and 1 x output rate ( auto-calibration enabled). the first conversion automatically begins at power-up using this default configuration. once the conversion is complete, a new word may be written into the device. the first 3 bits shifted into the device consist of two preen - able bits and one enable bit. as demonstrated in figure 3, the first three bits shifted into the device enable the device configuration and input channel selection. valid settings for these three bits are 000, 100 and 101. other combinations should be avoided. if the first three bits are 000 or 100, the following data is ignored ( don?t care) and the previously selected input channel and configuration remain valid for the next conversion. if the first 3 bits shifted into the device are 101, then the next 5 bits select the input channel for the next conversion cycle, see table 3. the first input bit following the 101 sequence ( sgl) determines if the input selection is differential ( sgl = 0) or single -ended ( sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input. for sgl = 1, one of 16 channels is selected as the positive input. the negative input is com for all single ended opera - tions. the remaining 4 bits ( odd, a2, a1, a0) determine which channel(s) is/are selected and the polarity ( for a differential input). the next serial input bit immediately following the input channel selection is the enable bit for the conversion configuration ( en2). if this bit is set to 0, then the next conversion is performed using the previously selected converter configuration. this is useful in systems using the same rejection/speed for all input channels and for backward compatibility with the ltc2418 / ltc2414 families of delta sigma adcs. a new configuration can be loaded into the device by setting en 2 = 1, see table 4. the first bit ( im) is used to select the internal temperature sensor. if im = 1, the following conversion will be performed on the internal temperature sensor rather than the selected input channel. the next 2 bits ( fa and fb) are used to set the rejection frequency. the final bit ( spd) is used to select either the 1x output rate if spd = 0 ( auto-calibration is enabled and the offset is continuously calibrated and removed from table 2. output data format differential input voltage v in * bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb bit 27 bit 26 bit 25 ? bit 0 v in * 0.5 ? v ref ** 0 0 1 1 0 0 0 ? 0 0.5 ? v ref ** ? 1lsb 0 0 1 0 1 1 1 ? 1 0.25 ? v ref ** 0 0 1 0 1 0 0 ? 0 0.25 ? v ref ** ? 1lsb 0 0 1 0 0 1 1 ? 1 0 0 0 1/0*** 0 0 0 0 ? 0 ?1lsb 0 0 0 1 1 1 1 ? 1 C0.25 ? v ref ** 0 0 0 1 1 0 0 ? 0 C0.25 ? v ref ** ? 1lsb 0 0 0 1 0 1 1 ? 1 C0.5 ? v ref ** 0 0 0 1 0 0 0 ? 0 v in * < C0.5 ? v ref ** 0 0 0 0 1 1 1 ? x**** *the differential input voltage v in = in+ ? in?. **the differential reference voltage v ref = ref+ ? ref?. ***the sign bit changes state during the 0 output code when the device is operating in the 2x speed mode. ****the underrange code is oxoffffxxx in 2x mode. downloaded from: http:///
ltc2498 19 2498fg for more information www.linear.com/ltc2498 applications information table 3. channel selection mux address channel selection sgl odd / sign a2 a1 a0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 com *0 0 0 0 0 in + in ? 0 0 0 0 1 in + in ? 0 0 0 1 0 in + in ? 0 0 0 1 1 in + in ? 0 0 1 0 0 in + in ? 0 0 1 0 1 in + in ? 0 0 1 1 0 in + in ? 0 0 1 1 1 in + in ? 0 1 0 0 0 in ? in + 0 1 0 0 1 in ? in + 0 1 0 1 0 in ? in + 0 1 0 1 1 in ? in + 0 1 1 0 0 in ? in + 0 1 1 0 1 in ? in + 0 1 1 1 0 in ? in + 0 1 1 1 1 in ? in + 1 0 0 0 0 in + in ? 1 0 0 0 1 in + in ? 1 0 0 1 0 in + in ? 1 0 0 1 1 in + in ? 1 0 1 0 0 in + in ? 1 0 1 0 1 in + in ? 1 0 1 1 0 in + in ? 1 0 1 1 1 in + in ? 1 1 0 0 0 in + in ? 1 1 0 0 1 in + in ? 1 1 0 1 0 in + in ? 1 1 0 1 1 in + in ? 1 1 1 0 0 in + in ? 1 1 1 0 1 in + in ? 1 1 1 1 0 in + in ? 1 1 1 1 1 in + in ? *default at power-up downloaded from: http:///
ltc2498 20 2498fg for more information www.linear.com/ltc2498 the final conversion result) or the 2 x output rate if spd = 1 ( offset calibration disabled, multiplexing output rates up to 15 hz with no latency). when im = 1 ( temperature measurement), spd will be ignored and the device will operate in 1 x mode. the configuration remains valid until a new input word with en = 1 ( the first 3 bits are 101) and en2 = 1 is shifted into the device.rejection mode ( fa , fb) the ltc2498 includes a high accuracy on-chip oscillator with no required external components. coupled with an integrated 4 th order digital lowpass filter, the ltc2498 rejects line frequency noise. in the default mode, the ltc2498 simultaneously rejects 50 hz and 60 hz by at least 87db. if more rejection is required, the ltc2498 can be configured to reject 50hz or 60hz to better than 110db.speed mode (spd) every conversion cycle, two conversions are combined to remove the offset ( default mode). this result is free from offset and drift. in applications where the offset is not critical, the auto-calibration feature can be disabled with the benefit of twice the output rate. while operating in the 2x mode ( spd = 1), the linearity and full-scale errors are unchanged from the 1 x mode performance. in both the 1 x and 2 x mode there is no latency. this enables input steps or multiplexer changes to settle in a single conversion cycle easing system overhead and increasing the effective conversion rate. during temperature measurements, the 1x mode is always used independent of the value of spd. temperature sensor the ltc2498 includes an integrated temperature sensor. the temperature sensor is selected by setting im = 1. during temperature readings, muxoutn / muxoutp remains connected to the selected input channel. the adc internally connects to the temperature sensor and performs a conversion. the digital output is proportional to the absolute tem - perature of the device. this feature allows the converter to perform cold junction compensation for external thermocouples or continuously remove the temperature effects of external sensors. the internal temperature sensor output is 28 mv at 27 c (300k), with a slope of 93.5 v/c independent of v ref . applications information table 4. converter configuration 1 0 en sgl odd a2 a1 a0 en2 im fa fb spd converter configuration 1 0 0 x x x x x x x x x x keep previous 1 0 1 x x x x x 0 x x x x keep previous (change channel) 0 0 0 x x x x x x x x x x keep previous 1 0 1 x x x x x 1 0 0 0 0 external input (see table 3) 50hz/60hz rejection, 1x 1 0 1 x x x x x 1 0 0 1 0 external input (see table 3) 50hz rejection, 1x 1 0 1 x x x x x 1 0 1 0 0 external input (see table 3) 60hz rejection, 1x 1 0 1 x x x x x 1 0 0 0 1 external input (see table 3) 50hz/60hz rejection, 2x 1 0 1 x x x x x 1 0 0 1 1 external input (see table 3) 50hz rejection, 2x 1 0 1 x x x x x 1 1 0 0 x measure temperature 50hz/60hz rejection, 1x 1 0 1 x x x x x 1 1 0 1 x measure temperature 50hz rejection, 1x 1 0 1 x x x x x 1 1 1 0 x measure temperature 60hz rejection, 1x downloaded from: http:///
ltc2498 21 2498fg for more information www.linear.com/ltc2498 applications information figure 4. internal ptat digital output vs temperature slope calibration is not required if the reference volt- age ( v ref ) is known. a 5 v reference has a slope of 314 lsbs 24 /c. the temperature is calculated from the output code ( dataout 24 ) for a 5 v reference using the following formula: t k = dataout 24 /314 in kelvin if a different value of v ref is used, the temperature output is : t k = dataout 24 ? v ref 1570 in kelvin if the value of v ref is not known, the slope is determined by measuring the temperature sensor at a known temperature t n (in k) and using the following formula: slope = dataout 24 /t n this value of slope can be used to calculate further tem- perature readings using: t k = dataout 24 /slope all kelvin temperature readings can be converted to t c (c) using the fundamental equation: t c = t k ? 273 serial interface timing modes the ltc2498?s 4- wire interface is spi and microwire compatible. this interface offers several flexible modes of operation. these include internal/external serial clock, 3- or 4- wire i/o , single cycle or continuous conversion. the following sections describe each of these timing modes in detail. in all cases, the converter can use the internal oscillator ( f o = low or f o = high) or an external oscillator connected to the f o pin. for each mode, the operating cycle , data input format, data output format, and performance remain the same. refer to table 5 for a summary. figure 5. absolute temperature error table 5. ltc2498 interface timing modes configuration sck source conversion cycle control d ata output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 6, 7 external sck, 3-wire i/o external sck sck figure 8 internal sck, single cycle conversion internal cs cs figures 9, 10 internal sck, 3-wire i/o, continuous conversion internal continuous internal figure 11 temperature (k) 0 dataout 24 60000 80000 100000 120000 140000 400 2498 f04 40000 0 300 200 100 20000 v cc = 5v v ref = 5v slope = 314 lsb 24 /k temperature (c) ?55 ?30 ?5 absolute error (c) 54 3 2 1 ?4 ?3 ?2 ?1 0 120 95 70 45 20 2498 f05 ?5 downloaded from: http:///
ltc2498 22 2498fg for more information www.linear.com/ltc2498 external serial clock, single cycle operation this timing mode uses an external serial clock to shift out the conversion result and cs to monitor and control the state of the conversion cycle, see figure 6.the external serial clock mode is selected during the power - up sequence and on each falling edge of cs . in order to enter and remain in the external sck mode of operation, sck must be driven low both at power-up and on each cs falling edge. if sck is high on the falling edge of cs , the device will switch to the internal sck mode. the serial data output pin ( sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the conversion is complete and the device is in the sleep state. independent of cs , the device automatically enters the sleep state once the conversion is complete; however, in order to reduce the power, cs must be high. when the device is in the sleep state, its conversion result is held in an internal static shift register. the device re- mains in the sleep state until the first rising edge of sck is seen while cs is low. the input data is then shifted in via the sdi pin on each rising edge of sck ( including the first rising edge). the channel selection and converter configuration mode will be used for the following conver - sion cycle . if the input channel or converter configuration is changed during this i/o cycle, the new settings take effect on the conversion cycle following the data input/ output cycle. the output data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32 nd rising edge of sck. on the 32 nd falling edge of sck, the device begins a new conversion and sdo goes high ( eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. applications information figure 6. external serial clock, single cycle operation hi-z 2498 f06 hi-z cs sck (external) sdi sdo conversion sleep data input/output conversion v cc f o ref + ref ? ch0ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 1516 23 7 38 37 1,3,4,5,6,31,32,33,39 36 34 reference voltage 0.1v to v cc analog inputs = external oscillator= internal oscillator 10f 0.1f ltc2498 2.7v to 5.5v 4-wirespi interface ?? ? ? ? ? ?? ? ? ? ? eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 bit 18 bit 17 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd don't care don't care msb sig ?0? downloaded from: http:///
ltc2498 23 2498fg for more information www.linear.com/ltc2498 applications information typically, cs remains low during the data output/input state. however, the data output state may be aborted by pulling cs high any time between the 1 st falling edge and the 32 nd falling edge of sck, see figure 7. on the rising edge of cs , the device aborts the data output state and immediately initiates a new conversion. in order to program a new input channel , 8 sck clock pulses are required. if the data output sequence is aborted prior to the 8 th falling edge of sck, the new input data is ignored and the previously selected input channel remains valid. if the rising edge of cs occurs after the 8 th falling edge of sck, the new input channel is loaded and valid for the next conversion cycle. if cs goes high between the 8 th falling edge and the 16 th falling edge of sck, the new channel is still loaded, but the converter configuration remains unchanged. in order to program both the input channel and converter configuration, cs must go high after the 16 th falling edge of sck ( at this point all data has been shifted into the device). external serial clock, 3-wire i/o this timing mode uses a 3- wire serial i/o interface. the con version result is shifted out of the device by an externally generated serial clock ( sck) signal, see figure 8. cs is permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected at the end of the power-on reset ( por) cycle. the por cycle is typically concluded 4 ms after v cc exceeds 2 v. the level applied to sck at this time determines if sck is internally gener- ated or externally applied. in order to enter the external sck mode, sck must be driven low prior to the end of the por cycle.since cs is tied low, the end-of-conversion ( eoc ) can be continuously monitored at the sdo pin during the convert and sleep states. eoc may be used as an interrupt to an external controller. eoc = 1 while the conversion is in figure 7. external serial clock, reduced output data length and valid channel selection hi-z 2498 f07 cs sck (external) sdi sdo conversion sleep data input/output sleep conversion v cc f o ref + ref ? ch0ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 1516 23 7 38 37 1,3,4,5,6,31,32,33,39 36 34 reference voltage 0.1v to v cc analog inputs = external oscillator= internal oscillator ltc2498 4-wirespi interface ?? ? ? ? ? ?? ? ? ? ? eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 29 bit 30 bit 31 1 2 3 4 5 6 7 8 1 0 en sgl a2 a1 a0 odd don't care don't care msb sig ?0? 10f 0.1f 2.7v to 5.5v downloaded from: http:///
ltc2498 24 2498fg for more information www.linear.com/ltc2498 applications information figure 8. external serial clock, 3-wire operation ( cs = 0) progress and eoc = 0 once the conversion is complete. on the falling edge of eoc , the conversion result is load- ing into an internal static shift register. the output data can now be shifted out the sdo pin under control of the externally applied sck signal. data is updated on the fall - ing edge of sck. the input data is shifted into the device through the sdi pin on the rising edge of sck. on the 32nd falling edge of sck, sdo goes high, indicating a new conversion has begun. this data now serves as eoc for the next conversion.internal serial clock, single cycle operation this timing mode uses the internal serial clock to shift out the conversion result and cs to monitor and control the state of the conversion cycle, see figure 9. in order to select the internal serial clock timing mode, the serial clock pin ( sck) must be floating or pulled high before the conclusion of the por cycle and prior to each falling edge of cs . an internal weak pull - up resistor is active on the sck pin during the falling edge of cs ; therefore, the internal sck mode is automatically selected if sck is not externally driven. the serial data output pin ( sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the con - verter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while the conversion is in progress and eoc = 0 if the device is in the sleep state when testing eoc , if the conversion is complete ( eoc = 0), the device will exit sleep state. in order to return to the sleep state and reduce the power consumption, cs must be pulled high before the device pulls sck high. when the device is using its own internal oscillator ( f o is tied low), the first rising edge of sck occurs 12 s ( t eoctest = 12 s) after the falling edge of cs . if f o is driven by an external oscillator of frequency f eosc , then t eoctest = 3.6/ f eosc . if cs remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is shifted out the sdo pin on the falling edge of sck. the serial input word ( sdi) is shifted into the device on the rising edge of sck. after the 32 nd rising edge of sck a new conversion au - tomatically begins. sdo goes high ( eoc = 1) and sck v cc f o ref + ref ? ch0ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 1516 23 7 38 37 1,3,4,5,6,31,32,33,39 36 34 reference voltage 0.1v to v cc analog inputs = external oscillator= internal oscillator ltc2498 3-wirespi interface ?? ? ? ? ? ?? ? ? ? ? eoc cs sck (external) sdi sdo 2498 f08 conversion sleep data input/output conversion bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd bit 18 bit 17 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 don't care don't care msb sig ?0? 10f 0.1f 2.7v to 5.5v downloaded from: http:///
ltc2498 25 2498fg for more information www.linear.com/ltc2498 applications information remains high for the duration of the conversion cycle. once the conversion is complete, the cycle repeats. typically, cs remains low during the data output state. however, the data output state may be aborted by pull - ing cs high any time between the 1 st rising edge and the 32 nd falling edge of sck, see figure 10. on the ris- ing edge of cs , the device aborts the data output state and immediately initiates a new conversion. in order to program a new input channel , 8 sck clock pulses are required. if the data output sequence is aborted prior to the 8 th falling edge of sck, the new input data is ignored and the previously selected input channel remains valid. if the rising edge of cs occurs after the 8 th falling edge of sck, the new input channel is loaded and valid for the next conversion cycle. if cs goes high between the 8 th falling edge and the 16 th falling edge of sck, the new channel is still loaded, but the converter configuration remains unchanged. in order to program both the input channel and converter configuration, cs must go high after the 16 th falling edge of sck ( at this point all data has been shifted into the device). internal serial clock, 3-wire i/o, continuous conversion this timing mode uses a 3- wire interface. the conversion result is shifted out of the device by an internally generated serial clock ( sck) signal, see figure 11. in this case, cs is permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. the internal serial clock mode is selected at the end of the power-on reset ( por) cycle. the por cycle is concluded approximately 4 ms after v cc exceeds 2 v. an internal weak pull-up is active during the por cycle; therefore, the internal serial clock timing mode is automatically selected if sck is floating or driven high. during the conversion, the sck and the serial data output pin ( sdo) are high ( eoc = 1). once the conversion is complete, sck and sdo go low ( eoc = 0) indicating the conversion has finished and the device has entered the sleep state. the device remains in the sleep state a minimum amount of time (1/2 the internal sck period) then immediately begins outputting and inputting data. figure 9. internal serial clock, single cycle operation 10f 0.1f 2.7v to 5.5v hi-z 2498 f09 cs sck (internal) sdi sdo conversion sleep data input/output conversion v cc f o ref + ref ? ch0ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 1516 23 7 38 37 1,3,4,5,6,31,32,33,39 36 34 reference voltage 0.1v to v cc analog inputs = external oscillator= internal oscillator ltc2498 4-wirespi interface ?? ? ? ? ? ?? ? ? ? ? eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 bit 18 bit 17 bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd don't care don't care msb sig ?0? optional10k v cc ltc2498 26 2498fg for more information www.linear.com/ltc2498 applications information figure 10. internal serial clock, reduced data output length with valid channel and configuration selection figure 11. internal serial clock, continuous operation 10f 0.1f 2.7v to 5.5v hi-z 2498 f10 cs sck (internal) sdi sdo conversion sleep data input/output conversion v cc f o ref + ref ? ch0ch7 ch8 ch15 com sck sdi sdo cs gnd 28 35 29 30 8 1516 23 7 38 37 1,3,4,5,6,31,32,33,39 36 34 reference voltage 0.1v to v cc analog inputs = external oscillator= internal oscillator ltc2498 4-wirespi interface ?? ? ? ? ? ?? ? ? ? ? eoc bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 29 bit 30 bit 31 bit 18 bit 17 1 2 3 4 5 6 7 8 9 10 11 12 13 16 1 0 en sgl a2 a1 a0 en2 im fa fb spd odd don't care don't care msb sig ?0? optional10k v cc ltc2498 27 2498fg for more information www.linear.com/ltc2498 the input data is shifted through the sdi pin on the ris- ing edge of sck ( including the first rising edge) and the output data is shifted out the sdo pin on the falling edge of sck. the data input/output cycle is concluded and a new conversion automatically begins after the 32 nd rising edge of sck. during the next conversion, sck and sdo remain high until the conversion is complete. the use of a 10k pull-up on sck for internal sck selection if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state if sck is floating. this will cause the device to exit the internal sck mode on the next falling edge of cs . this can be avoided by adding an external 10 k pull-up resistor to the sck pin. whenever sck is low, the ltc2498?s internal pull-up at sck is disabled. normally, sck is not externally driven if the device is operating in the internal sck timing mode. however, certain applications may require an external driver on sck. if the driver goes hi-z after outputting a low signal, the internal pull-up is disabled. an external 10k pull-up resistor prevents the device from exiting the internal sck mode under this condition. a similar situation may occur during the sleep state when cs is pulsed high-low-high in order to test the conversion status. if the device is in the sleep state ( eoc = 0), sck will go low. if cs goes high before the time t eoctest , the internal pull-up is activated. if sck is heavily loaded, the internal pull-up may not restore sck to a high state before the next falling edge of cs . the external 10 k pull-up resistor prevents the device from exiting the internal sck mode under this condition. preserving the converter accuracy the ltc2498 is designed to reduce as much as possible sensitivity to device decoupling, pcb layout, anti-aliasing circuits, line frequency perturbations, and temperature sensitivity. in order to achieve maximum performance a few simple precautions should be observed. digital signal levels the ltc2498?s digital interface is easy to use. its digital inputs ( sdi, f o , cs , and sck in external serial clock mode) accept standard cmos logic levels. internal hysteresis circuits can tolerate edge transition times as slow as 100 s . the digital input signal range is 0.5 v to v cc ? 0.5 v. during transitions, the cmos input circuits draw dynamic cur- rent. for optimal performance, application of signals to the serial data interface should be reserved for the sleep and data output periods. during the conversion period, overshoot and undershoot of fast digital signals applied to both the serial digital interface and the external oscillator pin ( f o ) may degrade the converter performance. undershoot and overshoot occur due to impedance mismatch of the circuit board trace at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to the input pin. for reference, on a regular fr-4 board, the propagation delay is approximately 183ps/inch. in order to prevent overshoot, a driver with a 1 ns transition time must be connected to the converter through a trace shorter than 2.5 inches. this becomes difficult when shared control lines are used and multiple reflections occur. parallel termination near the input pin of the ltc2498 will eliminate this problem, but will increase the driver power dissipation. a series resistor from 27 to 54 ( depend - ing on the trace impedance and connection) placed near the driver will also eliminate over/undershoot without additional driver power dissipation. for many applications, the serial interface pins ( sck, sdi, cs , f o ) remain static during the conversion cycle and no degradation occurs. on the other hand, if an external oscillator is used ( f o driven externally) it is active during the conversion cycle. moreover, the digital filter rejection is minimal at the clock rate applied to f o . care must be taken to ensure external inputs and reference lines do not cross this signal or run near it. these issues are avoided when using the internal oscillator. applications information downloaded from: http:///
ltc2498 28 2498fg for more information www.linear.com/ltc2498 applications information driving the input and referencethe input and reference pins of the ltc2498 are connected directly to a switched capacitor network. depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. each time a capacitor is switched between two of these pins, a small amount of charge is transferred. a simplified equivalent circuit is shown in figure 12. when using the ltc2498?s internal oscillator, the input capacitor array is switched at 123 khz. the effect of the charge transfer depends on the circuitry driving the input/ reference pins. if the total external rc time constant is less then 580 ns the errors introduced by the sampling process are negligible since complete settling occurs. typically, the reference inputs are driven from a low imped - ance source. in this case complete settling occurs even with large external bypass capacitors. the inputs ( ch0 to ch15, com), on the other hand, are typically driven from larger source resistances. source resistances up to 10 k may interface directly to the ltc2498 and settle completely ; however, the addition of external capacitors at the input terminals in order to filter unwanted noise ( anti-aliasing) results in incomplete settling. the ltc2498 offers two methods of removing these er- rors. the first is an automatic differential input current cancellation ( easy drive) and the second is the insertion of buffer between the muxout and adcin pins, thus isolating the input switching from the source resistance. automatic differential input current cancellation in applications where the sensor output impedance is low ( up to 10 k with no external bypass capacitor or up to 500 with 0.001 f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization is possible. for many applications, the sensor output impedance combined with external input bypass capacitors produces rc time constants much greater than the 580 ns required for 1 ppm accuracy. for example, a 10 k bridge driving a 0.1f capacitor has a time constant an order of magnitude greater than the required maximum. the ltc2498 uses a proprietary switching algorithm that forces the average differential input current to zero figure 12. ltc2498 equivalent analog input circuit in + in ? 10k internal switch network 10k c eq 12pf 10k i in ? ref + i ref + i in + i ref ? 2498 f12 switching frequencyf sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator ref ? 10k 100 input multiplexer external connection 100 muxoutp adcinp external connection muxoutn adcinn i in + ( ) avg = i in ? ( ) avg = v in(cm) ? v ref(cm) 0.5 ? r eq i ref + ( ) avg 1.5v ref + v ref(cm) ? v in(cm) ( ) 0.5 ? r eq ? v in 2 v ref ? r eq where: v ref = ref + ? ref ? v ref(cm) = ref + ? ref ? 2 ?? ?? ?? ?? v in = in + ? in ? , where in + and in ? are the selected input channels v in(cm) = in + ? in ? 2 ?? ?? ?? ?? r eq = 2.71m internal oscillator 60hz mode r eq = 2.98m internal oscillator 50hz/60hz mode r eq = 0.833 ? 10 12 ( ) /f eosc external oscillator downloaded from: http:///
ltc2498 29 2498fg for more information www.linear.com/ltc2498 applications information independent of external settling errors. this allows direct digitization of high impedance sensors without the need of buffers. the switching algorithm forces the average input current on the positive input ( i in + ) to be equal to the average input current in the negative input ( i in C ). over the complete conversion cycle, the average input current ( i in + C i in C ) is zero. while the differential input current is zero, the common mode input current ( i in + + i in C )/2 is proportional to the difference between the common mode input volt- age ( v in(cm) ) and the common mode reference voltage (v ref(cm) ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and com - mon mode input current are zero. the accuracy of the converter is not compromised by settling errors. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between v in(cm) and v ref(cm) . for a reference common mode voltage of 2.5 v and an input common mode of 1.5 v, the common mode input current is approximately 0.74a ( in simultaneous 50 hz/60hz rejection mode). this common mode input current does not degrade the accuracy if the source impedances tied to in + and in C are matched. mismatches in source impedance lead to a fixed offset error but do not effect the linearity or full scale reading. a 1% mismatch in a 1 k source resistance leads to a 74 v shift in offset voltage. in applications where the common mode input voltage varies as a function of the input signal level ( single ended type sensors), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2498, leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the dif - ference between the common mode input and common mode reference . 1% mismatches in 1 k source resistances lead to gain errors on the order of 15 ppm. based on the stability of the internal sampling capacitors and the ac - curacy of the internal oscillator, a one-time calibration will remove this error. in addition to the input sampling current, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1 na (10 na max) results in a small offset shift. a 1 k source resistance will create a 1v typical and a 10v maximum offset voltage.automatic offset calibration of external buffers/ amplifiers in addition to the easy drive input current cancellation, the ltc2498 enables an external amplifier to be inserted between the multiplexer output and the adc input, see figure 13. this is useful in applications where balanced source impedances are not possible. one pair of external buffers/amplifiers can be shared between all 17 analog inputs. the ltc2498 performs an internal offset calibration every conversion cycle in order to remove the offset and drift of the adc. this calibration is performed through a combination of front end switching and digital process - ing. since the external amplifier is placed between the multiplexer and the adc, it is inside this correction loop. this results in automatic offset correction and offset drift removal of the external amplifier. figure 13. external buffers provide high impedance inputs and amplifier offsets are automatically cancelled. C + C + 1/2 ltc60781/2 ltc6078 1 2 3 5 6 7 ? adc with easy drive inputs input mux muxoutpmuxoutn 17 2498 f13 ltc2498 analog inputs sdi sck sdo cs 1k 1k 0.1f 0.1f downloaded from: http:///
ltc2498 30 2498fg for more information www.linear.com/ltc2498 applications information the ltc6078 is an excellent amplifier for this function. it operates with supply voltages as low as 2.7 v and its noise level is 18 nv/ hz . the easy drive input technology of the ltc2498 enables an rc network to be added directly to the output of the ltc6078. the capacitor reduces the magnitude of the current spikes seen at the input to the adc and the resistor isolates the capacitor load from the op-amp output enabling stable operation.reference current similar to the analog inputs, the ltc2498 samples the differential reference pins ( ref + and ref C ) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. if incomplete set - tling occurs ( as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. for relatively small values of external reference capaci - tance ( c ref < 1 nf), the voltage on the sampling capacitor settles for reference impedances of many k? ( if c ref = 100pf up to 10 k will not degrade the performance), see figures 14, 15. in cases where large bypass capacitors are required on the reference inputs ( c ref > 0.01 f) full-scale and linear- ity errors are proportional to the value of the reference resistance. every ohm of reference resistance produces a full-scale error of approximately 0.5 ppm ( while operat - ing in simultaneous 50 hz/60hz mode), see figures 16 and 17. if the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67 ppm per 100 ? of reference resistance results, see figure 18. in applications where the input and reference common mode voltages are different, the errors increase. a 1 v difference in between common mode input and common mode reference results in a 6.7 ppm inl error for every 100? of reference resistance. in addition to the reference sampling charge, the reference esd projection diodes have a temperature dependent leak - age current . this leakage current, nominally 1 na (10 na max) results in a small gain error. a 100 ? reference resistance will create a 0.5v full scale error.normal mode rejection and anti-aliasing one of the advantages delta - sigma adcs offer over conventional adcs is on-chip digital filtering. combined with a large oversample ratio, the ltc2498 significantly simplifies anti-aliasing filter requirements. additionally, the input current cancellation feature allows external lowpass filtering without degrading the dc performance of the device. figure 14. +fs error vs r source at v ref (small c ref ) figure 15. ?fs error vs r source at v ref (small c ref ) r source () 0 +fs error (ppm) 50 70 90 10k 2498 f14 3010 40 60 8020 0 ?10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in ? = 1.25v f o = gnd t a = 25c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source () 0 Cfs error (ppm) C30 C10 10 10k 2498 f15 C50C70 C40 C20 0 C60C80 C90 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf downloaded from: http:///
ltc2498 31 2498fg for more information www.linear.com/ltc2498 applications information the sinc 4 digital filter provides excellent normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency ( f s ), see figures 19 and 20. the modulator sampling frequency is f s = 15,360hz while operating with its internal oscillator and f s = f eosc /20 when operating with an external oscillator of frequency f eosc . when using the internal oscillator, the ltc2498 is designed to reject line frequencies. as shown in figure 21, rejec - tion nulls occur at multiples of frequency f n , where f n is determined by the input control bits fa and fb ( f n = 50 hz or 60 hz or 55 hz for simultaneous rejection). multiples of the modulator sampling rate ( f s = f n ? 256) only reject figure 16. +fs error vs r source at v ref (large c ref ) figure 17. ?fs error vs r source at v ref (large c ref ) figure 18. inl vs differential input voltage and reference source resistance for c ref > 1f figure 19. input normal mode rejection, internal oscillator and 50hz rejection mode figure 20. input normal mode rejection, internal oscillator and 60hz rejection mode r source () 0 +fs error (ppm) 300 400 500 800 2498 f16 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 1f, 10f c ref = 0.1f c ref = 0.01f r source () 0 Cfs error (ppm) C200 C100 0 800 2498 f17 C300 C400 C500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 1f, 10f c ref = 0.1f c ref = 0.01f v in /v ref (v) ?0.5 inl (ppm of v ref ) 2 6 10 0.3 2498 f18 ?2?6 0 4 8 ?4?8 ?10 ?0.3 ?0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c c ref = 10f r = 1k r = 100 r = 500 differential input signal frequency (hz) 0 f s 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s 11f s 12f s input normal mode rejection (db) 2498 f19 0 ?10?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100?110 ?120 differential input signal frequency (hz) 0 f s input normal mode rejection (db) 2498 f20 0 ?10?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100?110 ?120 2f s 3f s 4f s 5f s 6f s 7f s 8f s 9f s 10f s downloaded from: http:///
ltc2498 32 2498fg for more information www.linear.com/ltc2498 figure 23. input normal mode rejection vs input frequency with input perturbation of 100% (60hz notch) applications information noise to 15 db ( see figure 22), if noise sources are present at these frequencies anti-aliasing will reduce their effects. the user can expect to achieve this level of performance using the internal oscillator, as shown in figures 23, 24, and 25. measured values of normal mode rejection are shown superimposed over the theoretical values in all three rejection modes. traditional high order delta - sigma modulators suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2498 third order modulator resolves this problem and guarantees stability with input signals 150% of full-scale. in many industrial applications, it is not uncommon to have mi - crovolt level signals superimposed over unwanted volt level error sour ces with several volts of peak-to-peak noise. figures 26 and 27 show measurement results for the rejection of a 7.5 v peak-to-peak noise source (150% figure 24. input normal mode rejection vs input frequency with input perturbation of 100% (50hz notch) figure 21. input normal mode rejection at dc figure 22. input normal mode rejection at f s = 256 ? f n figure 25. input normal mode rejection vs input frequency with input perturbation of 100% (50hz/60hz notch) input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2498 f23 0 ?20?40 ?60 ?80 ?100?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured datacalculated data input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2498 f24 0 ?20?40 ?60 ?80 ?100?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured datacalculated data input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2498 f25 0 ?20?40 ?60 ?80 ?100?120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured datacalculated data input signal frequency (hz) input normal mode rejection (db) 2498 f21 0 ?10?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100?110 ?120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc/5120 input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2498 f22 0 ?10?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100?110 ?120 downloaded from: http:///
ltc2498 33 2498fg for more information www.linear.com/ltc2498 applications information of full scale) applied to the ltc2498. from these curves, it is shown that the rejection performance is maintained even in extremely noisy environments. using the 2 x speed mode of the ltc2498 alters the rejec - tion characteristics around dc and multiples of f s . the device bypasses the offset calibration in order to increase the output rate. the resulting rejection plots are shown in figures 28 and 29. 1 x type frequency rejection can be achieved using the 2 x mode by performing a running average of the conversion results, see figure 30.output data rate when using its internal oscillator, the ltc2498 produces up to 7.5 samples per second ( sps) with a notch frequency of 60hz. the actual output data rate depends upon the length of the sleep and data output cycles which are controlled by the user and can be made insignificantly short. when operating with an external conversion clock ( f o connected to an external oscillator), the ltc2498 output data rate can be increased. the duration of the conversion cycle is 41036/f eosc . if f eosc = 307.2 khz, the converter behaves as if the internal oscillator is used.an increase in f eosc over the nominal 307.2 khz will translate into a proportional increase in the maximum output data rate ( up to a maximum of 100 sps). the increase in output rate leads to degradation in offset, full-scale error, and ef - fective resolution as well as a shift in frequency rejection. when using the integrated temperature sensor, the internal oscillator should be used ( f o = 0) or an external oscillator applied to f o , f eosc , should be set to 307.2khz max. figure 26. measure input normal mode rejection vs input frequency with input perturbation of 150% (60hz notch) figure 27. measure input normal mode rejection vs input frequency with input perturbation of 150% (50hz notch) figure 28. input normal mode rejection 2x speed mode figure 29. input normal mode rejection 2x speed mode input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2498 f26 0 ?20?40 ?60 ?80 ?100?120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) input frequency (hz) 0 normal mode rejection (db) 2498 f27 0 ?20?40 ?60 ?80 ?100?120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 input signal frequency (f n ) input normal rejection (db) 2498 f28 0 ?20?40 ?60 ?80 ?100?120 0 f n 2f n 3f n 4f n 5f n 6f n 7f n 8f n input signal frequency (f n ) input normal rejection (db) 2498 f29 0 ?20?40 ?60 ?80 ?100?120 250 248 252 254 256 258 260 262 264 downloaded from: http:///
ltc2498 34 2498fg for more information www.linear.com/ltc2498 applications information a change in f eosc results in a proportional change in the internal notch position. this leads to reduced differential mode rejection of line frequencies. the common mode rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the in + and in ? pins will continue to reject line frequency noise. an increase in f eosc also increases the effective dynamic input and reference current. external rc networks will continue to have zero differential input current, but the time required for complete settling (580 ns for f eosc = 307.2khz) is reduced, proportionally. once the external oscillator frequency is increased above 1 mhz ( a more than 3 x increase in output rate) the effective - ness of internal auto calibration circuits begins to degrade. this results in larger offset errors, full scale errors, and decreased resolution, see figures 31 to 38. figure 30. input normal mode rejection 2x speed mode with and without running averaging figure 31. offset error vs output data rate and temperature figure 32. +fs error vs output data rate and temperature figure 33.?fs error vs output data rate and temperature figure 34. resolution (noise rms 1lsb) vs output data rate and temperature figure 35. resolution (inl max 1lsb) vs output data rate and temperature differential input signal frequency (hz) 48 ?70?80 ?90 ?100?110 ?120 ?130 ?140 54 58 2498 f30 50 52 56 60 62 normal mode rejection (db) no average with running average output data rate (readings/sec) 0 ?3500 ?fs error (ppm of v ref ) ?3000 ?2000 ?1500 ?1000 0 10 2498 f33 ?2500 ?500 20 30 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 2498 f35 14 20 20 30 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) t a = 85c t a = 25c output data rate (readings/sec) ?10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 2498 f31 10 0 30 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 2498 f32 1000 3000 20 30 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 2498 f34 14 22 20 30 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock res = log 2 (v ref /noise rms ) t a = 85c t a = 25c downloaded from: http:///
ltc2498 35 2498fg for more information www.linear.com/ltc2498 applications information figure 37. resolution (noise rms 1lsb) vs output data rate and reference voltage figure 38. resolution (inl max 1lsb) vs output data rate and reference voltage figure 39. input range figure 36. offset error vs output data rate and reference voltage output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 20 24 10 2498 f37 14 22 20 30 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 2498 f38 14 20 20 30 v in(cm) = v ref(cm) v in = 0v ref ? = gnd f o = ext clock t a = 25c res = log 2 (v ref /inl max ) v cc = 5v, v ref = 2.5v v cc = v ref = 5v output data rate (readings/sec) 0 ?10 offset error (ppm of v ref ) ?5 5 10 20 10 2480 f36 0 15 20 30 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c v cc = 5v, v ref = 2.5v v cc = v ref = 5v v cc + 0.3v gnd gnd gnd ?0.3v gnd ?0.3v ?0.3v (a) arbitrary (b) fully differential (d) pseudo-differential unipolar in? or com grounded (c) pseudo differential bipolar in? or com biased v ref 2 v ref 2 v ref 2 v ref 2 v ref 2 ?v ref 2 ?v ref 2 ?v ref 2 selected in + ch selected in ? ch or com v cc v cc 2498 f39 v cc v cc downloaded from: http:///
ltc2498 36 2498fg for more information www.linear.com/ltc2498 package description please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1top mark (see note 6) 37 12 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 packageoutline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notchr = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) downloaded from: http:///
ltc2498 37 2498fg for more information www.linear.com/ltc2498 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number d 11/09 update tables 1 and 2 17, 18 e 7/10 revised typical application drawing added note 18 to digital inputs and digital outputs section 1 4, 5 f 2/12 updated title of ta 01b added h-grade 1 2, 4 g 11/14 clarified performance vs frequency, reduced external oscillator max frequency to 1mhz clarified input voltage range added underrange note to table 2. fixed location of sig bit changing state. 5, 8, 34, 353, 4, 15, 35 18 (revision history begins at rev d) downloaded from: http:///
ltc2498 38 2498fg for more information www.linear.com/ltc2498 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2006 lt 1114 rev g ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2498 part number description comments lt ? 1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift lt1790 micropower sot-23 low dropout reference family 0.05% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency s adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency s adc with differential inputs 0.8v rms noise, 2ppm inl ltc2411/ltc2411-1 24-bit, no latency s adcs with differential inputs in msop 1.45v rms noise, 2ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency s adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2415/ltc2415-1 24-bit, no latency s adcs with 15hz output rate pin compatible with the ltc2410 ltc2414/ltc2418 8-/16-channel 24-bit, no latency s adcs 0.2ppm noise, 2ppm inl, 3ppm total unadjusted errors 200a ltc2440 high speed, low noise 24-bit s adc 3.5khz output rate, 200nv rms noise, 24.6 enobs ltc2480 16-bit s adc with easy drive inputs, 600nv rms noise, programmable gain, and temperature sensor pin-compatible with ltc2482/ltc2484 ltc2481 16-bit s adc with easy drive inputs, 600nv rms noise, i 2 c interface, programmable gain, and temperature sensor pin-compatible with ltc2483/ltc2485 ltc2482 16-bit s adc with easy drive inputs pin-compatible with ltc2480/ltc2484 ltc2483 16-bit s adc with easy drive inputs, and i 2 c interface pin-compatible with ltc2481/ltc2485 ltc2484 24-bit s adc with easy drive inputs pin-compatible with ltc2480/ltc2482 ltc2485 24-bit s adc with easy drive inputs, i 2 c interface, and temperature sensor pin-compatible with ltc2481/ltc2483 ltc2496 16-bit 8-/16-channel s adc with easy drive input current cancellation pin-compatible with ltc2498/ltc2449 typical application external buffers provide high impedance inputs and amplifier offsets are automatically cancelled ? + ? + 1/2 lt6078 1/2 lt6078 1 2 3 5 6 7 ? adc with easy drive inputs input mux muxoutpmuxoutn 17 2498 ta02 ltc2498 analog inputs sdi sck sdo cs 1k 1k 0.1f 0.1f related parts downloaded from: http:///

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